1. Technical Field
This invention relates to a MOS (Metal-Oxide-Semiconductor) type transistor with metallic source and drain, and manufacturing processes for such a transistor.
Its applications are in the microelectronics fields, particularly for manufacturing integrated circuits with or without complementary transistors.
In particular, the invention is intended for use in applications requiring large scale integration of components, low energy consumption or high operating frequency.
2. State of Prior Art
FIG. 1 shows a diagrammatic cross section of a conventional MOS transistor at the end of an integration process for this transistor. The manufacturing process is the same for transistors with an n channel and transistors with p channels, apart from the doping steps.
The transistor in FIG. 1 comprises a p type silicon substrate 2 if the transistor has an n channel.
Two zones 4 and 6 are formed at a distance from each other on this substrate 2.
These zones 4 and 6 are n+ type diffused zones forming the transistor source and drain.
As can be seen in FIG. 1, zones 4 and 6 are prolonged by zones 8 and 10 respectively, that are nxe2x88x92 type diffused zones (less doped than zones 4 and 6).
Zones 8 and 10 form extensions of the source and drain zones under the transistor grid which will be discussed later.
The transistor in FIG. 1 also comprises two zones 12 and 14 that extend above zones 4 and 6 and approximately at the same level as zones 8 and 10 respectively (which are facing each other and are separated from each other only by a thin interval p type silicon).
These zones 12 and 14 are made of a metallic silicide and are self-aligned with respect to the transistor grid and with respect to the field insulation zones of this transistor, which will be discussed later.
Zones 12 and 14 form the shunt-metallisation of the transistor source and drain.
There is an electrically insulating layer 18 made of silica above the p type silicon zone 16 separating zones 8 and 10 from each other, extending also above these zones 8 and 10 and forming the insulation for the transistor grid.
There is a layer 20 made of polycrystalline silicon above layer 18.
There is a layer 22 above this layer 20 that is made of a metallic silicide and forms a shunt-metallisation.
The transistor grid is formed from these layers 20 and 22.
Furthermore, two electrically insulating spacers 24 and 26, for example made of silica or silicon nitride, extend on each side of the stack formed by the layers 20 and 22, as far as the grid insulation 18.
The transistor shown in FIG. 1 is electrically isolated from other identical transistors (not shown), also formed on the substrate 2, due to LOCOS type field insulation zones 28 and 30.
The entire structure thus obtained is covered by an insulating layer 32 made of silica glass doped with phosphorus and boron.
Two openings pass through this layer 32 on each side and open up on zones 12 and 14 respectively.
These two openings are filled with a metal by chemical vapour phase deposition and form the source and drain contacts 34 and 36 respectively.
The transistor in FIG. 1 also comprises two metallic interconnection layers 38 and 40 that are located on the surface of layer 32 and extend contacts 34 and 36 respectively.
The grid contact is not shown in FIG. 1.
FIG. 2 is a diagrammatic cross sectional view through another conventional MOS transistor.
This is a MOS on SOI (Silicon On Insulator) transistor that is shown at the end of its integration process.
The transistor in FIG. 2 is different from the transistor in FIG. 1 due to the fact that the layers 4 and 6 in it are much thinner and that these layers 4 and 6 and the silicon zone 42 between these layers are supported on a buried silicon oxide layer 44 that is itself supported on a silicon substrate 46.
The MOS transistors described above have a number of limitations related to their electronic characteristics and their dimensions on the substrate.
One of the main limitations is due to the value of the channel access resistance. This is due mainly to the internal resistance of the source and drain regions, and also to the quality of the source-channel and drain-channel contacts.
The access resistance to the transistor channels forms a constraint that has a negative influence, particularly on the operating speed performances and the consumption of the circuits on which they are installed.
The access resistance may be reduced by increasing the doping concentration in the source and drain regions. However, if the concentration is too high, there may be electrical perforation problems and this may be harmful to the life of the transistors.
The access resistance may also be reduced by increasing the thickness of the channel and the source and drain regions. A difficulty also arises in this case in the sense that a greater thickness of these regions can cause perforation of the transistor and leakage currents between the source and the drain. A greater thickness of the source and drain regions also causes an increase in the parasite source/substrate and drain/substrate capacitances.
A shallow depth of the channel and of the source and drain regions improves the behaviour of the transistor but increases the access resistance.
Furthermore, the production of contacts such as contacts 34 and 36 that can be seen in FIGS. 1 and 2, depends on the alignment precision of the manufacturing tools used. This constraint tends to prevent large scale integration of transistors and a reduction in their size.
FIG. 3 shows another type of known MOS transistor.
This type of transistor comprises a grid structure 57 comparable to the grid structure in FIGS. 1 and 2, described above. This structure lies above a very thin channel 95 defined in a substrate 50.
A metallic source and drain 92, 94 can be seen on each side of the grid structure. The source and drain are self-aligned on the grid structure 57 and extend partly underneath it. The reference 58 denotes an etching and polishing stop layer separating the source from the drain.
Furthermore, the source and drain are separated from the substrate 50 by an insulating layer 84. Extensions 88 and 90 of the insulating layer join the grid insulating layer and separate the source and drain regions 92, 94 from the channel region 95, respectively.
The extensions 88 and 90 are sufficiently thin to enable the passage of charge carriers, by the tunnel effect, from the source to the drain, through the channel in order to encourage the Coulomb blocking phenomenon.
The metallic nature of the source and drain, and their partial extension under the grid structure, tend to reduce the access resistance below the values of the transistors in FIGS. 1 and 2.
Furthermore, the self-alignment of the source and drain on the grid structure improves the compactness of the transistor and facilitates its miniaturisation.
A more detailed description of a transistor conform with FIG. 3 is given in document (1), for which the references are given at the end of the description. Other documents illustrating prior art or the manufacturing technologies used are also referenced at the end of the description.
Presentation of the Invention
The purpose of the invention is to propose a MOS transistor with performances better than previously described transistors, and that does not depend on conduction by the tunnel effect.
Another purpose is to propose a particularly compact transistor of this type suitable for large scale integration for the manufacture of circuits.
Yet another purpose is to propose such a transistor that has a particularly low access resistance and that is particularly resistant to electrical perforation or leakage phenomena.
Another purpose of the invention is to propose process for manufacturing such a transistor.
More precisely, the purpose of the inventions is a MOS transistor comprising:
a channel region made of semiconducting material above which there is a grid structure, the grid structure comprising a grid and insulating spacers coating the sides of the grid;
regions, called the source and drain extension regions, located on each side of the channel in direct contact with the semiconducting material of the channel, and arranged essentially under the grid structure, the extension regions being made of a non-insulating material,
metallic source and drain regions, in contact with the source and drain extension regions respectively, and extending partly under the grid structure.
The source and drain extension regions are made of a semiconducting or conducting material or an alloy or a compound of a semiconducting or conducting material, in other words, as described above, from a non-insulating material.
Furthermore, source and drain extension regions preferably extend at least partly under the grid, to optimise operation of the transistor.
Therefore, the transistor according to the invention is fundamentally different from the transistor in FIG. 3 and does not use the tunnel effect.
The transistor according to the invention operates like a device with a surface or buried inversion channel while the device in FIG. 3 is a quantum well MOS device using the Coulomb blocking effect, throughout the semiconducting volume under the grid.
The transistor according to the invention may be used as a voltage amplifying device.
The device in FIG. 3 may be used as a memory device or analogue electron counting device.
The transistor may also comprise an insulating layer designed to electrically isolate a solid part of a support substrate on which it is made. This is the case particularly when the transistor is made on an SOI (Silicon On Insulator) type substrate, in which the insulating layer is formed from a buried silicon oxide layer.
In particular, the insulating layer avoids parasite currents into the solid part of the substrate, and improves the electric isolation of the source and drain regions. It also limits their thickness.
According to another possibility, the transistor may comprise a discontinuous insulating layer, separating the assembly composed of the source and drain regions and the source and drain extension regions, from a solid part of the substrate. In this case, the channel may remain in electrical contact with the said solid part. The opening towards the subjacent solid substrate then enables parasite currents generated under the grid at the interface at the drain to escape.
Another purpose of the invention is a process for manufacturing a MOS transistor substrate, comprising:
a channel region made of a semiconducting material above which there is a grid structure, the grid structure comprising a grid and insulating spacers coating the sides of the grid,
regions called the source and drain extension regions made of a non-insulating material located on each side of the channel, in direct contact with the semiconducting material of the channel is made, and essentially extending under the grid structure,
metallic source and drain regions, in contact with the source and drain extension regions respectively.
The process comprises at least one substrate etching step to define part of the transistor selected among firstly the channel region, and secondly the source and drain extension regions; the etching extending partly under the grid structure.
In a first particular embodiment of the process, the etching may be used to fix the length of the assembly formed by the channel and source and drain extension regions.
In this case, the length is considered along the source-drain direction.
In this case, the etching concerns mainly the extension regions.
The process according to the invention can then more precisely comprise the following steps:
the formation of the grid on the semiconducting substrate, separated from the substrate by a grid insulation layer,
the implantation of doping impurities in the substrate, with a first dose, using the grid as the implantation mask to form the first doped zones on each side of the grid;
formation of insulating lateral spacers on the sides of the grid, covering part of the first doped zones, to form the grid structure;
etching of the substrate to eliminate doped zones not protected by the grid structure and eliminate part of the first doped zones under the grid structure, a remaining part of the first doped zones kept during etching, forming the source and drain extension regions;
formation of the source and drain, including the deposition of a metal that comes into contact with the source and drain extension regions respectively under the grid structure.
The etching may be done using any isotropic etching technique in order to eliminate part of the substrate under the grid structure.
However, this type of etching requires precise control over when it stops to avoid completely eliminating the semiconductor under the grid. More simply, this control is also necessary to not excessively attack the source and drain extension regions.
Furthermore, in order to enable more precise control of the etching, it would be possible to carry out a second doping at a dose rate higher than the dose rate in the first doping, using the grid structure as an implantation mask, after formation of the lateral spacers. This doping leads to the formation of second doped zones, extending on each side of the grid structure and partially under the grid structure. Selective etching of the second doped zones is then done, while preserving part of the first doped zones under the grid structure not affected by the second doping.
Selective etching in this case makes use of a difference in the etching rate between differently doped materials. Doping with a higher content will result in a semiconducting material that is more sensitive to the etching agents used.
The choice of etching agents and the implantation doses for the second doping are thus means of more precisely controlling the etching. It is also a means of controlling the size of the source and drain extension regions preserved during etching.
For example, the second doping may be a p+ type doping by implantation of germanium and/or boron. It may also be done by implanting carbon.
Furthermore, the etching may be followed by the formation of a metal silicide layer on part of the source and drain extension regions. This layer is formed on the exposed parts of the etching.
It is also possible to form a bond layer outside the source and drain extension regions, either at the same time or not at the same time as the silicide is formed.
The bond layer may be a metallic layer, all or partly nitrided, with the function of guaranteeing good mechanical contact between the metal and the source and drain regions and the previously formed structure.
For example, a titanium nitride layer can give a better electrical contact between the metal in the source drain regions and the semiconducting part of the extension regions.
According to a second possible embodiment of the process according to the invention that forms a variant to the embodiment described above, the process may comprise:
the formation of a grid structure on a substrate comprising a grid and insulating lateral spacers coating the grid;
etching of part of the substrate on each side of the grid structure, and partially under the grid structure, preserving a region of the substrate under the grid, forming the channel region;
placement of material on the sides opposite the channel region to form the source and drain extension regions respectively;
formation of source and drain, including the deposition of a metal in contact with the source and drain extension regions.
Placement of a material on the sides of the channel may denote growth of the material, for example by epitaxy, or a simple deposition of material. Apart from placement of the material, formation of extension regions may include heat treatment. This aspect will be described in more detail in the rest of the text.
According to the second possible embodiment of the process described above, the etching does not fix the dimensions of the source and drain extension regions but simply fixes the width of the channel in the source-drain direction.
Thus, only the channel is made of the semiconducting material of the substrate that supports the transistor. Therefore, the extension regions formed by growth after etching may be made of a different material, chosen freely.
The source and drain extension regions may be made, for example, by growing a material selected from among Si, SiGexCy, or a metal or metal oxide. When the material is a semiconductor, it may also be doped.
In particular, the source and drain extension regions can be formed by growing a doped material with exactly the same type of conductivity as the type of conductivity in the channel region, and with a greater concentration of doping impurities than the concentration of doping impurities in the channel region.
According to one variant, it is also possible to make the source and drain extension regions by the formation of metal silicide regions on the sides of the channel. The silicide regions that form the source and drain extension regions may, for example, be formed by the deposition of a metal and then by heat treatment to cause interdiffusion of metal with the silicon in the channel.
As in the first embodiment, the substrate can be etched selectively. In this case, before etching, impurities are implanted in the substrate in order to dope a layer of the substrate extending on each side of the grid structure and extending partially under the grid structure. Thus, all that is preserved from the doping is a region that will form the channel region. The implantation is followed by a selective etching to eliminate the layer of the substrate doped in this manner.
The additional formation of a contact layer (silicide) or a bond layer may also be envisaged as described above.
Other characteristics and advantages of the invention will become clearer after reading the following description with reference to the figures in the attached drawings. This description is given purely for illustrative purposes and is in no way restrictive.